1. Field of the Invention
The present invention relates to an information processing apparatus and method, a storage medium, a program and an imaging apparatus, and more particularly to an information processing apparatus and method, a storage medium, a program and an imaging apparatus, which are capable of improving an efficiency of data access and an instruction execution speed.
2. Description of Related Art
As disclosed in Japanese Patent Application Publication JP06-75854, there is an information processing apparatus whose instruction bus and data bus are separated. In the information processing apparatus of this type, instructions and data are transferred to and from a memory by using single virtual address space. Namely, a central processing unit (CPU) transfers an instruction to an instruction bus by using a virtual address space, and transfers data to a data bus by using the same virtual address space.
FIG. 1 shows an example of the structure of virtual and physical address spaces in the related art. In FIG. 1, the virtual address space 1 is an address space of a memory as viewed from the CPU and the physical address space is the space of a real memory. In the example shown in FIG. 1, although the virtual address space 1 and physical address space 2 are in one-to-one correspondence, some information processing apparatus uses a plurality of virtual address spaces and one physical address space in many-to-one correspondence.
In the example shown in FIG. 1, the virtual address space 1 includes: address areas 1-1 to 1-5 in which the virtual addresses of both instructions and data are disposed in a mixed manner in the order of address; and address areas 1-6 to 1-8 in which the virtual addresses of only data are disposed. In each area, instructions or data are disposed by a unit of a page size which is the minimum unit of address translation (e.g., 4 k bytes).
Pages of instructions and data disposed in the address area 1-1 of the virtual address space 1 are stored actually in an address area 2-1 of the physical address space 2. Pages of instructions and data disposed in the address area 1-2 of the virtual address space 1 are stored actually in an address area 2-2 of the physical address space 2. Pages of instructions and data disposed in the address area 1-3 of the virtual address space 1 are stored actually in an address area 2-6 of the physical address space 2. Pages of instructions and data disposed in the address area 1-4 of the virtual address space 1 are stored actually in an address area 2-4 of the physical address space 2.
Pages of instructions and data disposed in the address area 1-5 of the virtual address space 1 are stored actually in an address area 2-3 of the physical address space 2. Data pages disposed in the address area 1-6 of the virtual address space 1 are stored actually in an address area 2-5 of the physical address space 2. Data pages disposed in the address area 1-7 of the virtual address space 1 are stored actually in an address area 2-8 of the physical address space 2. Data pages disposed in the address area 1-8 of the virtual address space 1 are stored actually in an address area 2-7 of the physical address space 2.
As described above, in the virtual address space 1 and physical address space 2, virtual addresses and physical addresses are one-to-one correspondence. Accordingly, if the CPU designates a virtual address of an instruction or data by referring to the virtual address space 1, the designated virtual address is translated into a physical address. The instruction or data corresponding to the translated physical address is read from a memory and transferred to the CPU. In this manner, the CPU can execute an instruction corresponding to the designated virtual address.
In the related art, the same virtual address space shown in FIG. 1 is used for both instruction transfer and data transfer. Since long data to be used with an instruction is required to be stored as additional data, virtual addresses of instructions and data are disposed in the virtual address space in a mixed manner.
FIG. 2 shows an example of the structure of the address area 1-1 of the virtual address space 1 shown in FIG. 1. In the example shown in FIG. 2, the address area 1-1 includes virtual addresses for storing instructions 1 to 4, a jump instruction 1, data 1, data 2, and instructions 5 to 9, respectively in this order from the upper area. The CPU designates the virtual address of the address area 1-1 to execute the instruction stored for the virtual address. For example, the CPU designates the virtual addresses of the instructions 1 to 9 to sequentially execute the instructions starting from the instruction 1. In the example shown in FIG. 2, however, there are the virtual addresses of the data 1 and data 2 between the virtual addresses of the instructions 4 and 5. Therefore, as the instructions are sequentially executed starting from the instruction 1, the instruction 5 is required to be executed after the instruction 4. It is therefore necessary to dispose the jump instruction 1 for an unconditional branch from the instruction 4 to the instruction 5, immediately after the virtual address of the instruction 4.
As shown in FIG. 3, if the instruction 3 requires to read data 3 and the virtual address for storing the data 3 is stored at the virtual address at a distance d2 unable to be designated by the operand of the instruction 3 (the distance d2 remote from the virtual address for the instruction 3), then the operand of the instruction 3 cannot directly designate the data 3. In order to read the data 3, it is necessary to hold the data 2 as a relative address of the data 3 once at the virtual address at a distance d1 allowing the operand of the instruction 3 to directly designate. In this case, the instruction 3 reads the relative address of the data 3 held as the data 2, and by using the relative address, the instruction 4 can read the data 3. As compared to the direct designation, it is necessary to use two instructions and the data (relative address) held for the instruction.
If the instruction bus and the data bus are separated, the information processing apparatus is usually provided with an instruction cache (memory) 11 and a data cache (memory) 12, as shown in FIG. 4. In the example shown in FIG. 4, as the CPU designates the virtual address of the jump instruction 1 in the address area 1-1, a range e1 from the jump instruction 1, data 1, data 2 and to instruction 5 is registered in the instruction cache 11. As the CPU designates the virtual address of the data 1, the same range e1 is registered in the data cache 12. More specifically, not only the jump instruction 1 and instruction 5 but also the data 1 and 2 (hatched portion in FIG. 4) not used as the instruction are registered in the instruction cache 11. Similarly, not only the data 1 and 2 but also the jump instruction 1 and instruction 5 (hatched portion in FIG. 4) not used as the data are registered in the data cache 12.